Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - IP verilog

Search list

[USB develop] USBipcore

Description: usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
Platform: | Size: 155648 | Author: liu | Hits:

[VHDL-FPGA-Verilog] VERILOG_VERSION_PIC16C57

Description: VERILOG VERSION PIC16C57 是一个用于FPGA模拟PIC16C57的IP核，有帮助文件，介绍了如何测试使用这个IP核。用VERILOG语言编写的。-VERILOG VERSION PIC16C57 is a PIC16C57 for FPGA simulation of the IP core, has helped document describes how to test the use of the IP core.
Platform: | Size: 438272 | Author: friendz | Hits:

[VHDL-FPGA-Verilog] usb11

Description: 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。-Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
Platform: | Size: 414720 | Author: 戴求淼 | Hits:

[VHDL-FPGA-Verilog] can

Description: 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
Platform: | Size: 89088 | Author: 戴求淼 | Hits:

[Other Embeded program] CAST_jpeg_d-xact

Description: JPEG_D IP Core Verilog crypted source
Platform: | Size: 879616 | Author: Serg | Hits:

[VHDL-FPGA-Verilog] USB2.0IP

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档-Complete Verilog language developed by USB2.0 IP core source code, including documentation
Platform: | Size: 206848 | Author: 陈润 | Hits:

[VHDL-FPGA-Verilog] CAN_IP

Description: 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Platform: | Size: 61440 | Author: 普林斯 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera
Platform: | Size: 83968 | Author: ray | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[TCP/IP stack] TCPIP

Description: 用C实现的完整TCP/IP协议源代码,私家珍藏的宝贝-the code of TCP/IP protocol realized by C. It s very valuable.
Platform: | Size: 657408 | Author: joe | Hits:

[VHDL-FPGA-Verilog] can_verilog

Description: 基于verilog开发的　ｃａｎ　接口　ＩＰ　核已经调试通过附有说明-can ip
Platform: | Size: 45056 | Author: wangli | Hits:

[VHDL-FPGA-Verilog] fft_verilog

Description: FFT IP core 源码 状态控制机-FFT IP core
Platform: | Size: 7168 | Author: chris | Hits:

[Embeded-SCM Develop] pci.tar

Description: verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输-The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transactions originating on the PCI bus, the other one handling transactions originating on the WISHBONE bus.
Platform: | Size: 13253632 | Author: yemao | Hits:

[VHDL-FPGA-Verilog] i2c_master_slave_core

Description: I2C master/slave IP core
Platform: | Size: 2180096 | Author: zhanglh | Hits:

[Crack Hack] tripledes

Description: 3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
Platform: | Size: 31744 | Author: Yan, Like | Hits:

[VHDL-FPGA-Verilog] RealizationofdigitaldownconversionbyFPGA

Description: 介绍在FPGA 器件上如何实现单通道数字下变频（DDC）系统。利用编写VHDL 程序和调用部分IP 核相结合的方法研究了数字下变频的FPGA 实现方法,并且完成了其主要模块的仿真和调试,并进行初步系统级验证。-Introduced in the FPGA device on how to achieve the single-channel digital down conversion (DDC) system. VHDL procedures and the use of the preparation of some call a combination of IP core method of the FPGA digital down conversion method, and completed its main modules of simulation and debugging, and initial system-level verification.
Platform: | Size: 162816 | Author: 于银 | Hits:

[VHDL-FPGA-Verilog] i2c_ip

Description: I2C的ip核，Verilog实现，可以直接用在你的项目中。I2C是一种简单实用的通讯协议。-I2C' s ip nuclear, Verilog realization, you can directly use in your projects. I2C is a simple and practical protocol.
Platform: | Size: 2207744 | Author: caibaiyin | Hits:

[VHDL-FPGA-Verilog] 10100MIP

Description: 以太网10100M IP核Verilog源码(可综合)\以太网10-100M IP核Verilog源码，可综合-10100M IP Ethernet core Verilog source code (which can be integrated) \ 10-100M IP Ethernet core Verilog source code can be integrated
Platform: | Size: 740352 | Author: 打狗队 | Hits:

[Crack Hack] aes_core

Description: aes_core verified verilog ip core-aes_core verified verilog ip core
Platform: | Size: 11264 | Author: 邓婕 | Hits:

[VHDL-FPGA-Verilog] FFT_verilog

Description: verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
Platform: | Size: 618496 | Author: culun | Hits:
« 1 2 3 4 56 7 8 9 10 ... 18 »

CodeBus www.codebus.net